Explanation: The voltage gain is given by gmRd. So, gm become 2mS and a resistance of 4k Ω will be necessary.

Explanation: The input impedance can be found by performing a small signal analysis at the input node i.e. source of the MOSFET. Due to channel length modulation, the effect of ro would make the input impedance gm || 1/ro.

Explanation: The input current flows through the source of the MOSFET while the gate current is nearly equal to 0. Hence, the entire current coming out of the drain is due to the source current.

Explanation: The voltage gain due to M1 is gm1 * Rd || 1/gm2 since we find that the drain of M1 is connected to the source of M2 and the impedance looking into the source of a MOSFET is 1/gm2. Now, the voltage gain due to the 2nd CG stage is simply gm2*Rd2. Hence, the total voltage gain is a product of both the factors ie gm1 * Rd || 1/gm2 * gm2 * Rd2.

Explanation: The voltage gain due to M1 is gm1 * Rd || 1/gm2 || ro2 since we find that the drain of M1 is connected to the source of M2 and the impedance looking into the source of a MOSFET is 1/gm2 || ro2 due to the channel length modulation of M2. Now, the voltage gain due to the 2nd CG stage is simply gm2*Rd2. Hence, the total voltage gain is a product of both the factors ie gm1 * Rd || 1/gm2 * gm2 * Rd2.

Explanation: We develop a Thevenin’s equivalent w.r.t. node X and ground. But this is lengthy process. But then again, we can use the process as follows. For Thevenising, firstly we set Vdd and Vin to ground. Thereafter, we see that Rd and ro1 are in parallel to each other since they are connected from node X to ground. Next, we see that the impedance provided by M2 is 1/gm2 || ro2 but it again occurs from Node x to ground. Hence, all the impedances are parallel to each other and the total impedance at node X is Rd || ro1 || 1/gm2 || ro2.

Explanation: The voltage gain for the C.G. stage is simply gm * Rd1. The voltage gain of the next stage is – gm * Rd2. Note that, the ideal current source exhibits infinite output impedance and doesn’t affect but only increases the linearity of operation.

Explanation: increasing the transconductance or power supply is possible but we need to increase our power budget for both situations which is not possible. However, we can increase the aspect ratio of one MOSFET. This is because the total current entering into R1 is a sum of the currents originating from the drain of each MOSFET and they are equal to each other. Hence, scaling the aspect ratio is a plausible situation.

Explanation: To turn an NMOS on, we need to keep the voltage difference between the gate and the source greater than the threshold voltage. Hence, the gate potential should greater than the source potential by Vth.

Explanation: We note that all the MOSFET’s are in parallel. The output impedance of the ith MOSFET is given by roi. Hence, the total impedance at node x is simply R1 || ro1 || ro2…|| ron. Note that R1 is parallel to each MOSFET. This is because, while dining the output impedance, we set Vin and Vcc to zero. Note that R1 is connected from node X to ground, all the MOSFET’s are connected form node x to ground.