Q.1.
Which gates in Digital Circuits are required to convert a NOR-based SR latch to an SR flip-flop?
Q.2.
What characteristic will a TTL digital circuit possess due to its multi-emitter transistor?
Q.3.
What input should be given to “S” when SR flip – flop is converted to JK flip – flop?
Q.4.
What value is to be considered for a “don’t care condition”?
Q.5.
What is the group ofin 4 cells of a K – map called?
Q.6.
What will be the frequency of the output from a JK flip – flop, when J =K =and a clock with pulse waveform is given?
Q.7.
What gate is placed between clock input and the input of AND gate to convert a positive level triggered flip – flop to a negative level triggered flip – flop?
Q.8.
What will a TTL digital circuit possess due to the presence of a multi – emitter transistor?
Q.9.
How must the output of a gate act when it is LOW in a TTL circuit?
Q.10.
Which of the following gives the correct number of multiplexers required to build ax 1 multiplexer?
Q.11.
What must be the input given to “R” when SR flip – flop is converted to JK flip – flop?
Q.12.
What minimum distance is required for a single error correction according to Hamming’s analysis in Digital Electronics?
Q.13.
How many errors can the Digital Electronics parity method can find in a single word?
Q.14.
What is the group ofpresent in 8 cells of a K – map called?
Q.15.
Which of these flip – flops cannot be used to construct a serial shift register?
Q.16.
Which of these options represent the other name of Inter – Integrated logic?
Q.17.
Which of the following options is a Current – Mode logic used in Digital Circuits?
Q.18.
How many AND gates are required to construct a 4 – bit parallel multiplier if four 4 – bit parallel binary adders are given?
Q.19.
How many cycles of addition and shifting in a 4 – bit multiplier are required to perform multiplication using the shift method?
Q.20.
How many 4 – bit parallel binary adders will be required to construct a 4 – bit parallel multiplier?