Practice Verilog Multiple Choice Questions with Answers Quiz-1

Q.1.

Default value of a reg data type is ___.

0
1
x
z

Q.2.

The Verilog HDL code starts with the keyword_________

always
module
endmodule
items

Q.3.

If in1 = 4’band in2 = 4’bthen in1 + in2 equals

0111
x
0110
None of these

Q.4.

The most appropriate modeling style to implement Traffic light controller will be

Dataflow
Structural
Behavioral
Switch

Q.5.

Which of the following is a difference between a Function and a Task?

A Function can call another function; a Task cannot
A Function cannot call a task; a Task can call another task
A Function has one or more inputs; a Task has no inputs
A Function argument may be an output; a Task’s argument may only be an input

Q.6.

Which of the following loops are supported by verilog?

if-else loop
for loop
while loop
All the above

Q.7.

Verilog HDL is a case-sensitive language. All keywords are in _________.

lowercase
uppercase
either lower or uppercase
bold letters

Q.8.

{1'b2'b3'bwill result in

6'b 001001
6'b 001000
4'b 0010
4'b 0100

Q.9.

Which of the following is true about parameters?

The default size of a parameter in most synthesizers is the size of an integer, 32 bits
Parameters enable Verilog code to be compatible with VHDL
Parameters cannot accept a default value
All of the above

Q.10.

The keyword @posedge means

Transition from 0 to 1,x or z
Transition from x to 1
Transition from z to 1,x
All the above

Q.11.

If a variable is not assigned in all possible executions of an always statement then

A don’t care is inferred
A latch is inferred
The variable is set to 0
The synthesis process will fail

Q.12.

The keyword used for multiplying two bits in the form of gates is __________

AND
Or
and
none

Q.13.

RTL stands for _____________.

resistor‐transfer logic
register‐transfer logic
resistor‐transistor logic
register transistor logic

Q.14.

Which of the following is not an EDA tool?

Visual C++
Quartus II
Xilinx ISE
MaxPlus II

Q.15.

An entity can have more than one architecture.

True
False

Q.16.

Which of the following HDLs are IEEE standards?

VHDL and Verilog
C and C++
Altera and Xilinx
Quartus II and MaxPlus II

Q.17.

What is the full form of VHDL?

Verilog Hardware Description Language
Very High speed Description Language
Variable Hardware Description Language
Very high speed Integrated Circuit Hardware Description Language

Q.18.

When the number of inputs in a decoder iswhat will be the no. of outputs?

15
8
16
none

Q.19.

Which level of design abstraction requires logic circuit to write the Verilog HDL?

Gate level
Data flow
Behavioural
none

Q.20.

How many number of 3 to 8 decoders are used to design 4 todecoder?

5
8
2
4

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