Q.1.
The designers of Verilog wanted a language with syntax similar to the ________, which was already widely used in engineering software development
Q.2.
The symbol used for Logical AND operation is ______
Q.3.
The symbol used for bitwise AND operation is _____
Q.4.
In behavioral modeling the keyword used is _______
Q.5.
Different types of modelling in Verilog HDL are _____
Q.6.
The Verilog HDL code ends with the keyword_________
Q.7.
The full form of VHDL is _____________
Q.8.
The full form of HDL is _________________
Q.9.
Verilog is an
Q.10.
Which of the following vector part selection is considered ILLEGAL for the given example:wire [7:bus;reg [0:virtual_add;