Practice Counters Multiple Choice Questions with Answers Quiz-1

Q.1.

A counter with a modulus of 16 acts as a ________.

divide-by-8 counter
divide-by-16 counter
divide-by-32 counter
divide-by-64 counter

Q.2.

Integrated-circuit counter chips are used in numerous applications including:

timing operations, counting operations, sequencing, and frequency multiplication
timing operations, counting operations, sequencing, and frequency division
timing operations, decoding operations, sequencing, and frequency multiplication
data generation, counting operations, sequencing, and frequency multiplication

Q.3.

Which of the following statements best describes the operation of a synchronous up-/down-counter?

The counter can count in either direction, but must continue in that direction once started.
The counter can be reversed, but must be reset before counting in the other direction.
In general, the counter can be reversed at any point in its counting sequence.
The count sequence cannot be reversed, once it has begun, without first resetting the counter to zero.

Q.4.

What is the difference between a 7490 and a 7493?

7490 is a MOD-10, 7493 is a MOD-16
7490 is a MOD-16, 7493 is a MOD-10
7490 is a MOD-12, 7493 is a MOD-16
7490 is a MOD-10, 7493 is a MOD-12

Q.5.

Synchronous construction reduces the delay time of a counter to the delay of:

all flip-flops and gates
all flip-flops and gates after a 3 count
a single gate
a single flip-flop and a gate

Q.6.

The parallel outputs of a counter circuit represent the:

parallel data word
clock frequency
counter modulus
clock count

Q.7.

Any divide-by-N counter can be formed by using external gating to ________ at a predetermined number.

HIGH
reset
LOW
preset

Q.8.

Which of the following procedures could be used to check the parallel loading feature of a counter?

Preset the LOAD inputs, set the CLR to its active level, and check to see that the Q outputs match the values preset into the LOAD inputs.
Apply LOWs to the parallel DATA inputs, pulse the CLK input, and check for LOWs on all the Q outputs.
Apply HIGHs to all the DATA inputs, pulse the CLK and CLR inputs, and check to be sure that the Q outputs are all LOW.
Apply HIGHs to all the Q terminals, pulse the CLK, and check to see if the DATA terminals now match the Q outputs.

Q.9.

When two counters are cascaded, the overall MOD number is equal to the ________ of their individual MOD numbers.

product
sum
log
reciprocal

Q.10.

Select the response that best describes the use of the Master Reset on typical 4-bit binary counters.

When MR₁ and MR₂ are both HIGH, all Qs will be reset to zero.
When MR₁ and MR₂ are both HIGH, all Qs will be reset to one.
MR₁ and MR₂ are provided to synchronously reset all four flip-flops.
To enable the count mode, MR₁ and MR₂ must be held LOW.

Q.11.

A principle regarding most display decoders is that when the correct input is present, the related output will switch:

HIGH
to high impedance
to an open
LOW

Q.12.

A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does the counter go on the next clock pulse?

1101
1011
1111
0000

Q.13.

A ripple counter's speed is limited by the propagation delay of:

each flip-flop
all flip-flops and gates
the flip-flops only with gates
only circuit gates

Q.14.

Synchronous counters eliminate the delay problems encountered with asynchronous counters because the:

input clock pulses are applied only to the first and last stages
input clock pulses are applied only to the last stage
input clock pulses are not used to activate any of the counter stages
input clock pulses are applied simultaneously to each stage

Q.15.

One of the major drawbacks to the use of asynchronous counters is:

low-frequency applications are limited because of internal propagation delays
high-frequency applications are limited because of internal propagation delays
asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications
asynchronous counters do not have propagation delays and this limits their use in high-frequency applications

Q.16.

A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency if the input clock frequency is 60 MHz.

500 kHz
1,500 kHz
6 MHz
5 MHz

Q.17.

Why can a synchronous counter operate at a higher frequency than a ripple counter?

The flip-flops change one after the other.
The flip-flops change at the same time.
A synchronous counter cannot operate at higher frequencies.
A ripple counter is faster.

Q.18.

Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:

input clock pulses are applied only to the first and last stages.
input clock pulses are applied only to the last stage.
input clock pulses are applied simultaneously to each stage.
input clock pulses are not used to activate any of the counter stages.

Q.19.

A modulus-10 counter must have ________.

10 flip-flops
flip-flops
2 flip-flops
synchronous clocking

Q.20.

A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________.

15 ns
30 ns
45 ns
60 ns

Q.21.

How many flip-flops are required to construct a decade counter?

10
8
5
4

Q.22.

What is the difference between combinational logic and sequential logic?

Combinational circuits are not triggered by timing pulses, sequential circuits are triggered by timing pulses.
Combinational and sequential circuits are both triggered by timing pulses.
Neither circuit is triggered by timing pulses.

Q.23.

How many flip-flops are required to construct a decade counter?

10
8
5
4

Q.24.

How many natural states will there be in a 4-bit ripple counter?

4
8
16
32

Q.25.

Once an up-/down-counter begins its count sequence, it cannot be reversed.

True
False

Q.26.

Which segments of a seven-segment display would be required to be active to display the decimal digit 2?

a, b, d, e, and g
a, b, c, d, and g
a, c, d, f, and g
a, b, c, d, e, and f

Q.27.

How many AND gates would be required to completely decode ALL the states of a MOD-64 counter, and how many inputs must each AND gate have?

128 gates, 6 inputs to each gate
64 gates, 5 inputs to each gate
64 gates, 6 inputs to each gate
128 gates, 5 inputs to each gate

Q.28.

Which of the following statements are true?

Asynchronous events do not occur at the same time.
Asynchronous events are controlled by a clock.
Synchronous events do not need a clock to control them.
Only asynchronous events need a control clock.

Q.29.

MOD-6 and MOD-12 counters and multiples are most commonly used as:

frequency counters
multiplexed displays
digital clocks
power consumption meters

Q.30.

How many flip-flops are required to make a MOD-32 binary counter?

3
45
5
6

Support mcqgeeks.com by disabling your adblocker.