Which of the following is an invalid output state for an 8421 BCD counter?
How many different states does a 3-bit asynchronous counter have?
A multiplexed display being driven by a logic circuit:
List the state of each output pin of a 7447 if RBI = 0, LT = 1, A0 = 1, A1 = 0, A2 = 0, and A3 = 1.
For a one-shot application, how can HDL code be used to make a circuit respond once to each positive transition on its trigger input?
The terminal count of a 3-bit binary counter in the DOWN mode is ________.
The terminal count of a typical modulus-10 binary counter is ________.
A 4-bit counter has a maximum modulus of ________.
What is the difference between a 7490 and a 7492?
List which pins need to be connected together on a 7492 to make a MOD-12 counter.
Three cascaded modulus-5 counters have an overall modulus of ________.
Which segments (by letter) of a seven-segment display need to be active in order to display a digit 6?
Which of the following is an invalid state in an 8421 BCD counter?
Using four cascaded counters with a total of 16 bits, how many states must be deleted to achieve a modulus of 50,000?
A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(tot)) is ________.
What is meant by parallel load of a counter?
Which is not an example of a truncated modulus?
Four cascaded modulus-10 counters have an overall modulus of ________.
The hexadecimal equivalent of 15,536 is ________.
A seven-segment, common-anode LED display is designed for:
An asynchronous 4-bit binary down counter changes from count 2 to countHow many transitional states are required?
A BCD counter is a ________.
Which of the following groups of logic devices would be the minimum required for a MOD-64 synchronous counter?
After 10 clock cycles, and assuming that the DATA input had returned to 0 following the storage sequence, what values would be stored in Q4, Q3, Q2, Q1, Q0 of the register in Figure 7-5?
A MOD-16 ripple counter is holding the count 10012. What will the count be after 31 clock pulses?
Which of the following is an example of a counter with a truncated modulus?
Which of the following is a type of shift register counter?
What is the maximum delay that can occur if four flip-flops are connected as a ripple counter and each flip-flop has propagation delays of tPHL = 22 ns and tPLH = 15 ns?
In an HDL ring counter, many invalid states are included in the programming by:
To operate correctly, starting a ring counter requires: