Q.1.

A serial in/serial out shift register transfers data from one line of a parallel bus to another line one bit at a time.

Q.2.

The serial in/parallel out shift register transfers data from one parallel data bus to another parallel data bus one bit at a time across a single line.

Q.3.

________ counters are often used whenever pulses are to be counted and the results displayed in decimal.

Q.4.

A reliable method for eliminating decoder spikes is the technique called ________.

Q.5.

In order to check the CLR function of a counter, ________.

Q.6.

The technique used by one-shots to respond to an edge rather than a level is called ________.

Q.7.

A J-K flip-flop is reset and must stay reset after the clock pulse. This transition requires that ________.

Q.8.

A decade counter will count through decimal ________.

Q.9.

The ________ counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.

Q.10.

One method of troubleshooting involves ________ the circuit under test with a ________ or ________ and then observing the output to check for proper bit patterns.

Q.11.

In VHDL, if we need to remember a value it must be stored in a ________.

Q.12.

A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most significant bit is ________.

Q.13.

A glitch that appears on the decoded output of a ripple counter is often difficult to see on an oscilloscope because ________.

Q.14.

A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most significant bit is ________.

Q.15.

The term synchronous, as applied to counter operations, means that the counter is clocked such that each flip-flop in the counter is triggered at the same time.

Q.16.

A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most significant bit is ________.

Q.17.

The ________ counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.

Q.18.

A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most significant bit is ________.