A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?

Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (f_in) to the first flip-flop is 32 kHz, the output frequency (f_out) is ________.

The symbols on this flip-flop device indicate ________.

The advantage of a J-K flip-flop over an S-R FF is that ________.

The advantage of a J-K flip-flop over an S-R FF is that ________.

The 7476 and 74LS76 are both dual flip-flops.

All multivibrators require feedback.

Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.

A flip-flop's normal starting state when power is first applied to a circuit is always the SET state.

A D latch has one data-input line.

VHDL was created as a very flexible language and it allows us to define the operation of clocked devices in the code without relying on logic primitives.

Pulse-triggered flip-flops are identified by a bubble on the Q output terminal.

In VHDL, each instance of a component is given a name followed by a semicolon and the name of the library primitive.

Pulse-triggered or level-triggered devices are the same.

The propagation delay time t_PLH is measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output.

Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?

Latches are tristate devices whose state normally depends on asynchronous inputs.

Using knowledge from previous chapters, an S-R flip-flop circuit is easy to design.

The 7474 has two distinct types of inputs: synchronous and asynchronous.

The Q output of a flip-flop is normally HIGH when the device is in the "CLEAR" or "RESET" state.

Some flip-flops have invalid states.

The 555 timer can be used in either the astable or monostable modes.

Generally, a flip-flop's hold time is short enough so that its output will go to a state determined by the logic levels present at its synchronous control inputs just prior to the active clock transition.

A gated S-R flip-flop goes into the SET condition when S is HIGH, R is LOW, and EN is HIGH.

The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as a ________.

An astable multivibrator is a circuit that ________.

A D flip-flop is constructed by connecting an inverter between the SET and clock terminals.

It takes four flip-flops to act as a divide-by-4 frequency divider.

The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as logic standard primitives.

A latch can act as a contact-bounce eliminator.