In synchronous systems, the exact times at which any output can change state are determined by a signal commonly called the ________.

The S-R flip-flop has no invalid or unused state.

A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ mS.

A positive edge-triggered flip-flop will accept inputs only when the clock ________.

How many flip-flops are required to produce a divide-by-128 device?

The key to edge-triggered sequential circuits in VHDL is the ________.

The S-R flip-flop has no invalid or unused state.

The S-R flip-flop has no invalid or unused state.

A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ mS.

A flip-flop is in the CLEAR condition when .

A J-K flip-flop and associated waveforms are shown below. The circuit is operating properly.

PRESET and CLEAR inputs are normally synchronous.

A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ mS.

A positive edge-triggered flip-flop will accept inputs only when the clock ________.

Assume an latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ________.