Q.1.

What is the function of a buffer circuit?

Q.2.

What is the preset condition for a ring shift counter?

Q.3.

The primary purpose of a three-state buffer is usually:

Q.4.

Which is not characteristic of a shift register?

Q.5.

What is the difference between a ring shift counter and a Johnson shift counter?

Q.6.

To keep output data accurate, 4-bit series-in, parallel-out shift registers employ a ________.

Q.7.

What is a recirculating register?

Q.8.

When is it important to use a three-state buffer?

Q.9.

On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2 = 1, and Q3 =On the sixth clock pulse, the sequence is ________.

Q.10.

The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses?

Q.11.

What is a shift register that will accept a parallel input, or a bidirectional serial load and internal shift features, called?

Q.12.

On the third clock pulse, a 4-bit Johnson sequence is Q0 = 1, Q1 = 1, Q2 = 1, and Q3 =On the fourth clock pulse, the sequence is ________.

Q.13.

A bidirectional 4-bit shift register is storing the nibbleIts input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing ________.

Q.14.

A 4-bit ring counter is loaded with a singleThe frequency of any given output is ________.

Q.15.

Assume a LOW logic level is placed on the SHIFT/LOAD input of a 74195 shift register. The output will change ________.

Q.16.

Shifting a binary number to the left by one position is equivalent to ________.

Q.17.

Assume a 4-bit Johnson counter is initially cleared. After the first clock pulse the output isAfter the next clock pulse the output will be ________.

Q.18.

A type of shift register in which the Q or Q output of one stage is not connected to the input of the next stage is ________.

Q.19.

A Johnson counter, constructed with N flip-flops, has how many unique states?

Q.20.

Assume a 4-bit parallel in/serial out shift register is loaded with a binary number. How many clock pulses are required after the parallel load has occurred before the first bit in the sequence appears on the serial output line?