Practice Flip-Flops And Timers Multiple Choice Questions with Answers Quiz-2

Q.1.

Which of the following describes the operation of a positive edge-triggered D-type flip-flop?

If both inputs are HIGH, the output will toggle.
The output will follow the input on the leading edge of the clock.
When both inputs are LOW, an invalid state exists.
The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.

Q.2.

Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

Q.3.

One example of the use of an S-R flip-flop is as a(n) _________.

Q.4.

Edge-triggered flip-flops must have _________.

Q.5.

What is one disadvantage of an S-R flip-flop?

Q.6.

An astable multivibrator is a circuit that:

Q.7.

What is another name for a one-shot?

Q.8.

The 555 timer can be used in which of the following configurations?

Q.9.

If an input is activated by a signal transition, it is _____________.

Q.10.

An S-R flip-flop can be triggered by ______, ______, or ________.

Q.11.

A basic S-R flip-flop can be constructed by cross-coupling which basic logic gates?

Q.12.

An S-R NAND latch with both of its inputs LOW has an output that is _____________.

Q.13.

What is another name for a one-shot?

Q.14.

If an input is activated by a signal transition, it is _____________.