Explanation: SPARC have RISC architecture which has a simple instruction set but MC68020, MC68030, 8086 have CISC architecture which is more complex than CISC.

Explanation: von Neumann architecture shares bus between program memory and data memory whereas Harvard architecture have a separate bus for program memory and data memory.

Explanation: SRAM access data in approximately 4ns because of its flip-flop arrangement of transistors whereas the data access time in DRAM is approximately 60ns since it has a single capacitor for one-bit storage.

Explanation: Zig-zag package of memory is a plastic package used for DRAM. The leads of this package are arranged in a zigzag manner.

Explanation: The coherency is a major challenge in designing the cache memory. The cache has to be designed by solving the problem of data coherency while remaining hardware and software compatible.

Explanation: By using the bidirectional ports, each master can monitor the line and confirm its expected state and if it is not matched, a mismatch or collision had occurred which will discontinue the transmission by the master.

Explanation: RCLK provides an input clock for the receiver part of the UART. RD is the read signal. MR is the master reset pin and DDIS is used to control bus arbitration logic.

Explanation: The linear codec is also known as pulse code modulation which is commonly used in the telecommunications industry.

Explanation: The common method for connecting the peripheral to the processor is the external interrupts. The external interrupts are provided through the external pins which are connected to the peripherals.

Explanation: The switching between user mode and supervisor mode provides protection for the processor, that is, the different modes in the software interrupt allows the memory and the associated code and data to be protected from each other.

Explanation: The asynchronous exception is the one in which an external event causes an exception and is independent of the instruction flow. On the other hand, the synchronous exceptions are synchronised, that is, it is caused by the instruction flow.

Explanation: The external interrupts generates the fast interrupt routine exception in which the external interrupt is synchronised with the processor clock.

Explanation: The time slicing works by switching task in regular periodic points in time, that is, any task that needs to run next will have to wait until the current time slice is completed.

Explanation: The ISR can send the message for the tasks and it is a part of RTOS kernel.

Explanation: A pNA+ network manager is a networking option which can provide the TCP/IP communication over a large variety of media such as the FDDI and the ethernet.

Explanation: The swap file of Windows 3.1 have a size of 25 Mbytes and thus limits the amount of virtual memory that it can support.

Explanation: Microcontrollers are the CPUs which have integrated memory and peripherals but microprocessor possesses external chips for memory.

Explanation: The EDD or earliest due date is based on Jackson’s rule. The Jackson’s rule states that for a given a set of n independent tasks, any algorithm that executes the tasks in the order of nondecreasing deadlines is optimal with respect to reducing the maximum lateness. EDF is the earliest deadline first, LL is the least laxity and the LST is the least slack time first.

Explanation: The in-circuit emulation does not have the ability to get a hundred individual signal cables into the probe. This problem comes under the physical limitation of the probe, that is as the density of the processor increases the available sockets which provide good electrical contacts is becoming harder which causes a restriction to the probe.

Explanation: The errors in the linear buffering include the loss of data especially during the regular sampling which can be avoided by the pointers that are checked against certain values and this result is used for fetching more data. These points are known as the low water mark and the high water mark.