Execute – instruction from prepared data-path reads from registry bank, shifts operand to ALU and writes generated result to dominant register.

Explanation: Pipeline is linear, which means that in simple data processing processor executes one instruction in single clock cycle which while individual instruction takes three clock cycles.

Explanation: The ARM7 family members have different packages, such as DIP(Dual In Line), QFP(Quad Flap Package), LLC(Leadless Chip Carrier) they all have 40 pins that are dedicated to different functions. Especially 8051 has a Quad Flap Package.

Explanation: The AVR7 processor wakes up from power down mode via external interrupt or BOD.

Explanation: It is the first series of ARM7. This memory is used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It can also be programmed in system via serial port.

Explanation: The vectored Interrupt controller accepts all the interrupts request inputs and categorizes them as Fast Interrupt Request, Vectored Interrupt Request, and Non Vectored IQR as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.

Explanation: Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.

Explanation: The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals.

Explanation: The converters are single 10-bit successive approximation analog to digital converters. While ADC0 has 6 channels, ADC1 has 8 channels. And DAC output voltage is the vref voltage.

Explanation: Pipelining is a technique for implementing instruction level parallelism within a single processor. Pipelining attempts to keep every part of the processor busy with some instructions, by dividing incoming instructions into the series of sequential steps.

Explanation: The signal BTAN[1:0] is placed by one bus cycle. This pipelining should be taken into account when these signals are being decoded. The value of BTRAN[1:0] indicates whether the next bus cycle is a data cycle or an address cycle.

Explanation: BWAIT pin can be used to extend memory access in whole cycle increments. BWAIT is driven by the selected slave during the low phase of BCLK.

Explanation: ARM7100 has two programmable duty ratio 96KHz clock output which is intended to be used as drivers for DC to DC converter in the PSU subsystems.

Explanation: A 3-stage pipelining is used, so instructions are executed in three stages: Fetch, Decode, Execute.

Explanation: The ARM7TDMI-S processor has 4 types of memory cycle: Non sequential cycle, Sequential cycle, cp processor register transfer cycle, internal cycle.