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Master Computer Applications
1000 Computer Organization Architecture
Quiz 2
Solution
Q.1.
For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution?
a) ANSA
b) Super-scalar
c) ISA
d) All of the mentioned
Q.2.
What is the full form of ISA?
a) Industry Standard Architecture
b) International Standard Architecture
c) International American Standard
d) None of the mentioned
Q.3.
Which of the following is the fullform of CISC?
a) Complex Instruction Sequential Compilation
b) Complete Instruction Sequential Compilation
c) Computer Integrated Sequential Compiler
d) Complex Instruction Set Computer
Q.4.
The reason for the cells to lose their state over time is ________
a) Use of Shift registers
b) The lower voltage levels
c) Usage of capacitors to store the charge
d) None of the mentioned
Q.5.
In order to read multiple bytes of a row at the same time, we make use of ______
a) Memory extension
b) Cache
c) Shift register
d) Latch
Q.6.
The difference in the address and data connection between DRAM’s and SDRAM’s is _______
a) The requirement of more address lines in SDRAM’s
b) The usage of a buffer in SDRAM’s
c) The usage of more number of pins in SDRAM’s
d) None of the mentioned
Q.7.
The chip can be disabled or cut off from an external connection using ______
a) ACPT
b) RESET
c) LOCK
d) Chip select
Q.8.
The controller multiplexes the addresses after getting the _____ signal.
a) INTR
b) ACK
c) RESET
d) Request
Q.9.
The data is transferred over the RAMBUS as _______
a) Blocks
b) Swing voltages
c) Bits
d) Packets
Q.10.
The memory devices which are similar to EEPROM but differ in the cost effectiveness is ______
a) CMOS
b) Memory sticks
c) Blue-ray devices
d) Flash memory
Q.11.
The flash memory modules designed to replace the functioning of a hard disk is ______
a) RIMM
b) FIMM
c) Flash drives
d) DIMM
Q.12.
In a 4M-bit chip organisation has a total ofexternal connections, then it has _______ address if 8 data lines are there.
a) 2
b) 5
c) 9
d) 8
Q.13.
What does ISO stands for?
a) International Software Organisation
b) Industrial Software Organisation
c) International Standards Organisation
d) Industrial Standards Organisation
Q.14.
The bit used to signify that the cache location is updated is ________
a) Flag bit
b) Reference bit
c) Update bit
d) Dirty bit
Q.15.
During a write operation if the required block is not present in the cache then ______ occurs.
a) Write miss
b) Write latency
c) Write hit
d) Write delay
Q.16.
While using the direct mapping technique, in abit system the higher order 5 bits are used for ________
a) Id
b) Word
c) Tag
d) Block
Q.17.
The bit used to indicate whether the block was recently used or not is _______
a) Reference bit
b) Dirty bit
c) Control bit
d) Idol bit
Q.18.
The number successful accesses to memory stated as a fraction is called as _____
a) Access rate
b) Success rate
c) Hit rate
d) Miss rate
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