Explanation: HDLs (Hardware Description Languages) are used to describe hardware for any electronic circuit or system; whereas other computer programming languages execute a program on the computer itself.

Explanation: VHDL and Verilog are the only two HDLs endorsed by IEEE. C andC++ are not HDLs. Altera and Xilinx are devices on which these HDLs can be used. Quartus II and MaxPlus II are the platforms for simulation of hardware described by HDLs.

Explanation: Digital systems are very complex and this complexity is increasing day by day. Some characteristics like propagation delay, concurrent processing and interconnection of parts can’t be captured with traditional languages.

Explanation: An HDL supports the hierarchical design process. It can describe the circuit or hardware at every possible level, whether it is gate level or switch level or RTL level.

Explanation: Due to the complexity of digital circuits, we need to process all the instructions at the same time. For example, current can flow in the two branches at the same time which can affect the output of the system, if sequentially processed.

Explanation: By using HDL, we specify what we need. We can optimize the circuit by using HDLs. ASIC(Application Specific IC) is a very complex which may consist of millions of transistors. So, we need concurrent execution first of all. Apart from that, we need timing information and other complex features of the digital system too.

Explanation: The syntax and whole structure of VHDL code is based upon ADA programming language whereas Verilog HDL finds its origin from C language.

Explanation: A circuit specified in VHDL can be implemented in different chips and is compatible with CAD tools provided by all companies. Therefore, without any modification, we can use VHDL code anywhere. This is the biggest advantage because digital circuit technology changes rapidly.

Explanation: VHDL is a strongly typed language i.e. we have to write a long code to define operations.

Explanation: Verilog HDL is a case sensitive language which means ‘a’ and ‘A’ means different if you are coding in Verilog.