Q.1.
A sequential logic can’t be executed by concurrent statements only.
- a) True
- b) False
Q.2.
Which of the following sequential circuit doesn’t need a clock signal?
- a) Flip flop
- b) Asynchronous counter
- c) Shift register
- d) Latch
Q.3.
The following timing diagram shows ______ flip flop.
- a) T flip-flop
- b) D flip-flop
- c) SR flip-flop
- d) JK flip-flop
Q.4.
The process used for implementation of sequential logic in VHDL is called ______ process.
- a) Sequential process
- b) Combinational process
- c) Clocked process
- d) Unclocked process
Q.5.
Why do we need to define clock signal in the sensitivity list of the process?
- a) To trigger the statement as soon as there is some event on clock
- b) To trigger the clock signal as soon as there is some event on input
- c) To trigger the clock signal as soon as there is some event on output
- d) To trigger the statement as soon as there is some event on input
Q.6.
A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 andThis condition is known as _______
- a) Switching condition
- b) Master slave condition
- c) Race around condition
- d) Edge triggered condition
Q.7.
Which of the following method is not used to remove the race around condition in a flip flop?
- a) Using level triggered flip flop
- b) Using master slave flip flop
- c) Using edge triggered flip flop
- d) All of the above are used to remove the race around
Q.8.
Which of the following attribute is generally used in implementation of sequential circuits?
- a) ‘STABLE
- b) ‘LENGTH
- c) ‘LAST_EVENT
- d) ‘EVENT
Q.9.
Which of the following line is correct for detecting positive edge of a clock?
- a) IF (clk’EVENT AND clk = ‘0’)
- b) IF (clk’EVENT AND clk = ‘1’)
- c) IF (clk’EVENT OR clk = ‘0’)
- d) IF (clk’EVENT OR clk = ‘1’)
Q.10.
A user doesn’t want to use the IF statement for detecting clock edge. It is possible to do the same by using any other keyword in VHDL.
- a) True
- b) False